1. Field of the Invention
The present invention relates to multiplexers and, in particular, to a compact multiplexer design that reduces the number of transistors required for a tree structure multiplexer.
2. Discussion of Prior Art
A multiplexer performs a binary decode of input signals to select a single output from a number of potential outputs. For purposes of discussion in this document, multiplexer input signals will be referred to as "addresses" and multiplexer output signals will be referred to as "selects".
For purposes of simplicity, two prior art multiplexers having only two addresses will be described. Those skilled in the art will appreciate that multiplexers having more than two addresses are common. Both of the described multiplexers can be designed for either a select logic low or a select logic high.
A first conventional multiplexer design, and the most simple, uses NOR-gates or NAND-gates. FIGS. 1A-1D show a NOR-gate design that generates four selects from two addresses. In this case, a select is enabled when it is high. FIGS. 1A-1D combine to show both the logic-level and transistor-level schematics for each of the four respective selects.
FIGS. 2A-2D combine to show the corresponding NAND-gate design. In this case, a select is enabled when it is low.
A second multiplexer design is commonly referred to as a tree structure. In this design, logically identical transistors are combined. For example, transistor M1 in FIG. 1A is combined with transistor M5 in FIG. 1B and transistor M9 in FIG. 1C is combined with transistor M13 in FIG. 1D to arrive at the tree structures shown in FIGS. 3 and 3B, respectively. Similarly, transistor M4 in FIG. 2A is combined with transistor M8 in FIG. 2B and transistor M12 in FIG. 2C is combined with transistor M16 in FIG. 2D to arrive at the tree structures shown in FIGS. 4A and B, respectively.